Please use this identifier to cite or link to this item:
https://elibrary.khec.edu.np:8080/handle/123456789/665
Title: | REAL-TIME ENCRYPTION AND DECRYPTION USING FPGA |
Authors: | Ajay Shrestha (750404) Deepa Rajbhandari (750409) Rijan Shrestha (750424) Simran Giri (750427) |
Advisor: | Er. Krishna Prasad Gaihre |
Keywords: | PYNQ FPGA, ESP32 WROOM, Real-time, Encryption, Decryption, IoT |
Issue Date: | Aug-2023 |
College Name: | Khwopa Engineering College |
Level: | Bachelor's Degree |
Degree: | BE Electronics and Communication Engineering |
Department Name: | Department of Electronics and Communication Engineering |
Abstract: | This project “REAL-TIME ENCRYPTION AND DECRYPTION USING FPGA” presents a novel approach to real-time encryption and decryption using the PYNQ FPGA board in conjunction with the ESP32 WROOM module. Our project focuses on achieving secure and efficient data communication, leveraging the capabilities of both the PYNQ FPGA board and the ESP32 WROOM. We implement AES encryption algorithms to ensure data privacy during transmission, and we demonstrate real-time performance by integrating hardware acceleration on the PYNQ FPGA board. By offloading the cryptographic operations onto dedicated hardware blocks within the FPGA, the system achieves reduced latency and minimized processing overhead on the wireless communication module. We applied optimization techniques, including pipelining and parallelization, to maximize the throughput of the encryption process while adhering to the resource constraints of the FPGA. Additionally, we explore the integration of the AES-enabled FPGA module into wireless communication systems, highlighting its compatibility with various wireless communication protocols. The combination of these technologies offers a powerful solution for secure realtime data exchange, with potential applications in IoT, wireless communication, and other domains requiring secure data transfer. In order to compare our FPGA-accelerated technique with software-based AES implementations, we analyzed latency, throughput, and resource usage. The outcomes highlight the potential of FPGA-based AES encryption in boosting the security and effectiveness of wireless communication by demonstrating significant improvements in latency and data rate. We demonstrate the effectiveness and efficiency of our real-time encryption and decryption system through experimental validation, demonstrating its potential to improve data security. |
URI: | https://elibrary.khec.edu.np/handle/123456789/665 |
Appears in Collections: | Electronics & communication Engineering Report |
Files in This Item:
File | Description | Size | Format | |
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REAL-TIME ENCRYPTION AND DECRYPTION USING FPGA.pdf Restricted Access | 1.96 MB | Adobe PDF | View/Open Request a copy |
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